As computing systems become increasingly sophisticated, digital signal processing (DSP) systems are making the transition from fixed-point arithmetic to floating-point arithmetic, which provides freedom from overflow and underflow and which simplifies interfacing to the rest of the computing system. Such computing systems typically use the Institute of Electrical and Electronics Engineers (IEEE) 754-Standard Floating-Point Arithmetic, which supports multiple rounding modes.
One type of unit that can perform both add and subtract operations simultaneously is a fused add-subtract floating-point unit, such as the unit described in U.S. Pat. No. 8,161,090, issued to Swartzlander, et al. on Apr. 17, 2012, which is incorporated herein by reference in its entirety. Such fused add-subtract floating-point units reduce circuit area and power consumption as compared to discrete floating-point implementations.